FPSADMIN.CTM_REF_SUMMARY_VALUES_L2

FACILITY

Facility is included in almost every join in the DWH so this represents a definitive split. A route must have all steps on tools in the same facility. A tool must process all lots in the same facility. If your site has multiple buildings where lots run on routes using tools in multiple buildings then everything should be one facility. For example, multiple Fab buildings. But if your site has independent facilities like Fab and Test and Assembly where lot may progress from one to the next but on different routes then these should be different facilities. Since this column is in virtually every table it is critical that the value here is exactly matches what is in the MES if the MES has facility. Use facility_display for the display friendly name displayed in applications. See site_name comment for client/site/facility example. (* inherited from FPSINPUT.GEN_FACILITIES)

PRD

Prd determines the route which is used to process the lot in the facility and what tools, recipes, durables, etc. can be used at each step. Prd also determines the next facility for the lot when it finishes its route. For detailed information on prd vs. planprd see table comments in RTG_PLANPRDS. (* inherited from FPSINPUT.RTG_PRDS)

PLANPRD

Planning product used for all planning purposes. All lots with the same planprd are interchangeable to ship to the customer regardless of their prd, route, technology, wafer size, etc. For detailed information on prd vs. planprd see table comments in RTG_PLANPRDS. (* inherited from FPSINPUT.RTG_PLANPRDS)

ROUTE

Route that has threading requirements (* inherited from FPSINPUT.RTG_STEP_THREADING)

STEP

A single processing step within a route representing a single tool visit. Step is often a very complex string and should rarely be displayed. Instead we should use process_display. (* inherited from FPSINPUT.RTG_ROUTE_STEPS)

BANK

Lots which are not on a route are considered in a bank and the bank name indicates why the lot is off route. Bank must be NA for lots which are on a route. Our standard filter for active lots is bank = NA. (* inherited from FPSINPUT.RTG_BANKS)

PRTY_CTM_GROUP

This is one of the primary keys of our CTM tables. We use this group rather than the priority because we often have several different priorities which are close and are expected to have the same cycle time. (* inherited from FPSINPUT.WIP_PRIORITIES)

LOT_GROUP

Lot_group is a grouping of lot_family and is the highest grouping in the lot type hierarchy. There should be only a few values for lot_group, i.e. Prod, Dev, TW. We group WIP and moves by lot_group on the dashboard and we group cycle time calculations by lot_group so this is an important field. (* inherited from FPSINPUT.WIP_LOT_GROUPS)

IS_NONSTD

Our column to indicate non-standard processing at the step. For example, an experiment or a chain that is only active at a particular step or set of steps and then goes back to being normal for the route. If an experiment is severe enough that it affects the final product and has to be planned separately then it will be its own prd or planprd. (* inherited from FPSBASE.WIP_LOT_HIST)

SEQ_NUM

Sequence number of step in route (* inherited from FPSINPUT.RTG_ROUTE_STEPS)

PROCESS

Process defines what occurs at a step. Different steps can share the same process if they are identical. Process should normally determine allowed tools and recipe although it can be overridden by step, route, prd, lot, and experiment for exceptions. Each process is dynamically assigned to one or more eqp_type-process_family combinations with use_pct. One process_family is determined to be primary. If grouping is done correctly, a process should only be one eqp_group with no crossover. (* inherited from FPSINPUT.RTG_PROCESSES)

PROCESS_FAMILY

See https://help.inficonims.com/display/DW/Guide+to+Process+Families. (* inherited from FPSINPUT.RTG_PROCESS_FAMILIES)

ROUTE_FAMILY

Route_family indicates that all routes within the family have similar or even identical steps and have the same segments. At facilities where various prds share the same route it is likely that the route will be the route_family. This is sometimes referred to as the main process flow. It is used on Segment Summary and Line Viewer to group similar routes. (* inherited from FPSINPUT.RTG_ROUTE_FAMILIES)

PRTY_CTM_FACTOR

Factor to multiply cycle time for this priority group compared to other groups if not known. For example, if this factor is 1.5 and we know the CTM is 6 hours for another priority group whose factor is 1.0 then we would estimate it to be 9 hours for this group. (* inherited from FPSINPUT.WIP_PRTY_CTM_GROUPS)

STEP_SEC_NOHOLD_FOR_WSF

The FOR_WSF columns are used in populating WIP_STEP_FUTURE. This is based on the CTM_COLUMN_FOR_WIP_STEP_FUT column in GEN_FACILITIES. For example, if the value of that column is 7D_WAVG then we use the 7D_WAVG cycle times for WSF. (* inherited from FPSBASE.CTM_SUMMARY)

STEP_SEC_FOR_WSF_IF_TAKE

STEP_SEC_FULL_WAVG

STEP_SEC_LONG_WAVG

STEP_SEC_7D_WAVG

STEP_SEC_7D_MED

STEP_SEC_2D_WAVG

AVG_WIP_FULL

AVG_WIP_7D

FIFO_STEP_SEC

TARGET_STEP_SEC

COMMIT_STEP_SEC

EST_LINE_YIELD_PCT

Estimated line yield percent for the route-step. Leave blank for the default of no loss expected. A value of 99.5 means we expected 1 unit out of 200 to be lost. (* inherited from FPSINPUT.RTG_ROUTE_STEPS)

LINE_YIELD_PCT_TO_EOL

Line yield percentage to end of line is the percentage of units expected to successfully complete the remaining steps on the route. Normally we multiply the line yield of all remaining steps for the Capacity Model but entering a value in this OVR table manually overrides that calculated number. (* inherited from FPSINPUT.RTG_ROUTE_STEP_EQPTYPE_OVR)

SORT_YIELD_PCT_TO_EOL

STEP_SEC_NOHOLD_FOR_WSF_TO_EOL

This is the expected seconds from the current step to the end of line not including time on hold. WIP_STEP_FUTURE is used for upcoming arrivals and should predict as if the lot will not go on hold unless it is known that it will. The result is that the predictions are reasonably correct for lots that do not go on hold or where we know the future hold - but very wrong for a few lots that go on hold that we do not expect. In contrast, WIP_FLUSH which is used for prediction completion of the route and all future routes will use the entire STEP_SEC including average hold. (* inherited from FPSBASE.CTM_SUMMARY)

STEP_SEC_FULL_WAVG_TO_EOL

STEP_SEC_LONG_WAVG_TO_EOL

STEP_SEC_7D_WAVG_TO_EOL

STEP_SEC_7D_MED_TO_EOL

STEP_SEC_7D_MED_NOT_ISKIP

STEP_SEC_2D_WAVG_TO_EOL

FIFO_STEP_SEC_TO_EOL

This can be used for critical ratio to avoid the following situation. Lot A of prd A and lot B of prd B are both at the same step on the same route. Plan CT for A is 40 plan CT for B is 60. Due date for A is in 41 days. Due date for B is in 59 days. Normal CR says A is one day ahead and B is one day behind so run B first. But this is insane because both are on the same route with exactly the same steps coming up and B is only "behind" because of a lower expectation. We should run A first. If we use FIFO then both are something like 50 days CT and A is 9 days behind and B is 9 days ahead. However there is a problem with this strategy because we would basically let B sit around and do nothing for 20 days until it was also 40 days and then have to run it at the same rate. So this is not perfect either. (* inherited from FPSBASE.CTM_SUMMARY)

FIFO_QUEUE_SEC

PROC_SEC_FOR_EOL

TARGET_STEP_SEC_TO_EOL

TARGET_QUEUE_SEC

COMMIT_STEP_SEC_TO_EOL

COMMIT_QUEUE_SEC

UNIT_INT_SEC_TO_EOL

The idea here is that a 1 wafer lot will progress a bit faster than a 25 wafer lot because it will save 24 wafer intervals at each step where wafers are processed individually. This column stores the number of seconds we expect to save for each wafer until the end of the line. In WIP_FLUSH we simply add or subtract this time based on whether the qty was higher or lower than the default in GEN_FACILITIES. We do not include lots which have been split in this adjustment since we expect they will be merged. For example, the CT to EOL is 30 days using our default of 20 wafers and this unit_int_sec_to_eol is 0.4 days. A lot with 19 wafers would get a revised estimate of 29.6. A lot with 18 wafers would get 29.2 and so on down to a lot with a single wafer at 22.4 days. On the other hand, our default can be less than the max so a lot with 21 wafers would get a revised estimate of 30.4 and so on up to a 25 wafer lot at 32 days. (* inherited from FPSBASE.CTM_SUMMARY)

EST_SMP_PCT

Smp_pct tells you what percentage of the lots complete on a tool. Some sites skip steps by jumping over them so we see the lot move from step 3 to step 5 and we only know that it jumped step 4 because step 4 is on the route between 3 and 5. Other sites skip steps by moving lots into them and then moving them out a second later so we see a move from 3 to 4 at 11:11:11 and a move from 4 to 5 at 11:11:12. We do not care how it is done but just that the lot did not process at step 4 -- and to be more specific that no tool capacity is required to process this lot at step 4 and no cycle time is accumulated at step 4. (* inherited from FPSBASE.WIP_GOAL_LOT_SHIFT)