FPSADMIN.CTM_SUMMARY_PRD_ROUTE_STEP

FACILITY

Facility is included in almost every join in the DWH so this represents a definitive split. A route must have all steps on tools in the same facility. A tool must process all lots in the same facility. If your site has multiple buildings where lots run on routes using tools in multiple buildings then everything should be one facility. For example, multiple Fab buildings. But if your site has independent facilities like Fab and Test and Assembly where lot may progress from one to the next but on different routes then these should be different facilities. Since this column is in virtually every table it is critical that the value here is exactly matches what is in the MES if the MES has facility. Use facility_display for the display friendly name displayed in applications. See site_name comment for client/site/facility example. (* inherited from FPSINPUT.GEN_FACILITIES)

PRD

Prd determines the route which is used to process the lot in the facility and what tools, recipes, durables, etc. can be used at each step. Prd also determines the next facility for the lot when it finishes its route. For detailed information on prd vs. planprd see table comments in RTG_PLANPRDS. (* inherited from FPSINPUT.RTG_PRDS)

ROUTE

Route that has threading requirements (* inherited from FPSINPUT.RTG_STEP_THREADING)

STEP

A single processing step within a route representing a single tool visit. Step is often a very complex string and should rarely be displayed. Instead we should use process_display. (* inherited from FPSINPUT.RTG_ROUTE_STEPS)

BANK

Lots which are not on a route are considered in a bank and the bank name indicates why the lot is off route. Bank must be NA for lots which are on a route. Our standard filter for active lots is bank = NA. (* inherited from FPSINPUT.RTG_BANKS)

IS_TW

Our standard filter to exclude test wafers is is_tw = N but what we really mean with this filter is to exclude any lots that do not add value for the facility. Lots which add value including sellable, development, and engineering and these lot groups should have is_tw set to N. Lots which do not add value are commonly grouped together and named "test wafers" which is why this flag is named is_tw. These include true test wafers like monitors and quals and dummies but also could include virtual lots used for training or testing, bare wafers, or really anything else including in the MES as a lot which does not add value. All of these lot groups should have is_tw set to Y. You could argue that the is_tw field might be more accurately named is_value or is_valuable or is_prod_eng_dev but is_tw is generally clear to most people. Plus it has the advantage that it is short which is nice given how frequently we use the is_tw = N filter. (* inherited from FPSINPUT.WIP_LOT_GROUPS)

SEQ_NUM

Sequence number of step in route (* inherited from FPSINPUT.RTG_ROUTE_STEPS)

REVERSE_SEQ_NUM

IS_MAIN_ROUTE

Y indicates the route is the main processing route for PRD. N indicates it is a rework or alternate route. (* inherited from FPSBASE.RTG_ACTIVE_PRD_ROUTES_BASE)

PROCESS

Process defines what occurs at a step. Different steps can share the same process if they are identical. Process should normally determine allowed tools and recipe although it can be overridden by step, route, prd, lot, and experiment for exceptions. Each process is dynamically assigned to one or more eqp_type-process_family combinations with use_pct. One process_family is determined to be primary. If grouping is done correctly, a process should only be one eqp_group with no crossover. (* inherited from FPSINPUT.RTG_PROCESSES)

PROCESS_FAMILY

See https://help.inficonims.com/display/DW/Guide+to+Process+Families. (* inherited from FPSINPUT.RTG_PROCESS_FAMILIES)

PROCESS_MODULE

WIP_MODULE is used to credit moves and set goals. See comments on the module column in GEN_MODULES for info on this column and how it relates to eqp_module and mnt_module. (* inherited from FPSBASE.RTG_ROUTE_STEPS_PLUS)

ROUTE_FAMILY

Route_family indicates that all routes within the family have similar or even identical steps and have the same segments. At facilities where various prds share the same route it is likely that the route will be the route_family. This is sometimes referred to as the main process flow. It is used on Segment Summary and Line Viewer to group similar routes. (* inherited from FPSINPUT.RTG_ROUTE_FAMILIES)

WAFER_SIZE

If the facility only has one wafer size then this column should be null in both RTG_PRDS and EQP_TYPES. If the facility has more than one wafer size then a value of null in EQP_TYPES means that those tools can run all wafer sizes. See column IS_ANY_WAFER_SIZE for details. (* inherited from FPSINPUT.GEN_WAFER_SIZES)

IS_STAGING_STEP

We expect large amounts of WIP and long cycle times at staging steps. We still calculate cycle time like any other step but the important difference is that lots currently at a staging step are not counted as normal coming lots to future steps. Instead we show them in a special column labeled From Staging. (* inherited from FPSINPUT.RTG_ROUTE_STEPS)

NUM_JOBS_COMP_FULL

QTY_COMP_FULL

NUM_LOTS_ISKIP_FULL

QTY_ISKIP_FULL

NUM_LOTS_DSKIP_FULL

QTY_DSKIP_FULL

NUM_LOTS_DTONLY_FULL

QTY_DTONLY_FULL

TOTAL_STEP_SEC_FULL

AVG_WIP_FULL

WHY_PROC_FULL

WHY_OTHERS_FULL

WHY_SKIP_FULL

STEP_SEC_FULL_WAVG

HOLD_SEC_COMP_FULL_WAVG

BLOCK_SEC_COMP_FULL_WAVG

WAIT_SEC_COMP_FULL_WAVG

DISP_SEC_COMP_FULL_WAVG

PROC_SEC_COMP_FULL_WAVG

ENDED_SEC_COMP_FULL_WAVG

STEP_SEC_ISKIP_FULL_WAVG

ISKIP is immediate skip. Since this value measures how long lots which immediately skip the step are at the step, by definition it should be less than 60 seconds. Therefore it can basically be ignored but it is necessary for data integrity to make sure every second is counted. (* inherited from FPSBASE.CTM_SUMMARY)

ISKIP_RATE_FULL

WAIT_SEC_DSKIP_FULL_WAVG

DSKIP is delayed skip. These are lots which wait at the step for longer than 60 seconds but do not process on a tool. For example, at a metrology step where a newer lot arrives and the older lot is moved out without being measured. All bank cycle time fits in the DSKIP columns. (* inherited from FPSBASE.CTM_SUMMARY)

HOLD_SEC_DSKIP_FULL_WAVG

DSKIP_RATE_FULL

WAIT_SEC_DTONLY_FULL_WAVG

DTONLY is delta only which is when a lot changes qty but remains at the same step. This could be a scrap or split or merge. Since CTM is weighted by qty, it is critical that we have a separate record in WIP_STEP_HIST before and after a change in qty so each period of time can be weighted appropriately. The time during DTONLY is counted towards the total time but it is not counted as a move. (* inherited from FPSBASE.CTM_SUMMARY)

HOLD_SEC_DTONLY_FULL_WAVG

DTONLY_RATE_FULL

NUM_LOTS_MOVED_FULL

QTY_MOVED_FULL

SMP_RATE_FULL

SMP_PCT_FULL

ISKIP_PCT_FULL

DSKIP_PCT_FULL

STEP_SEC_FULL_WAVG_NOT_ISKIP

STEP_SEC_COMP_FULL_WAVG

NUM_JOBS_COMP_LONG

QTY_COMP_LONG

NUM_LOTS_ISKIP_LONG

QTY_ISKIP_LONG

NUM_LOTS_DSKIP_LONG

QTY_DSKIP_LONG

NUM_LOTS_DTONLY_LONG

QTY_DTONLY_LONG

TOTAL_STEP_SEC_LONG

AVG_WIP_LONG

WHY_PROC_LONG

WHY_OTHERS_LONG

WHY_SKIP_LONG

STEP_SEC_LONG_WAVG

HOLD_SEC_COMP_LONG_WAVG

BLOCK_SEC_COMP_LONG_WAVG

WAIT_SEC_COMP_LONG_WAVG

DISP_SEC_COMP_LONG_WAVG

PROC_SEC_COMP_LONG_WAVG

ENDED_SEC_COMP_LONG_WAVG

STEP_SEC_ISKIP_LONG_WAVG

ISKIP_RATE_LONG

WAIT_SEC_DSKIP_LONG_WAVG

HOLD_SEC_DSKIP_LONG_WAVG

DSKIP_RATE_LONG

WAIT_SEC_DTONLY_LONG_WAVG

HOLD_SEC_DTONLY_LONG_WAVG

DTONLY_RATE_LONG

NUM_LOTS_MOVED_LONG

QTY_MOVED_LONG

SMP_RATE_LONG

SMP_PCT_LONG

ISKIP_PCT_LONG

DSKIP_PCT_LONG

STEP_SEC_LONG_WAVG_NOT_ISKIP

STEP_SEC_COMP_LONG_WAVG

NUM_JOBS_COMP_7D

QTY_COMP_7D

NUM_LOTS_ISKIP_7D

QTY_ISKIP_7D

NUM_LOTS_DSKIP_7D

QTY_DSKIP_7D

NUM_LOTS_DTONLY_7D

QTY_DTONLY_7D

NUM_LOTS_AT_LEAST_ONE_HOLD_7D

QTY_AT_LEAST_ONE_HOLD_7D

TOTAL_STEP_SEC_7D

AVG_WIP_7D

WHY_PROC_7D

WHY_OTHERS_7D

WHY_MEDS_7D

WHY_SKIP_7D

STEP_SEC_7D_WAVG

HOLD_SEC_COMP_7D_WAVG

BLOCK_SEC_COMP_7D_WAVG

WAIT_SEC_COMP_7D_WAVG

DISP_SEC_COMP_7D_WAVG

PROC_SEC_COMP_7D_WAVG

ENDED_SEC_COMP_7D_WAVG

STEP_SEC_ISKIP_7D_WAVG

ISKIP_RATE_7D

WAIT_SEC_DSKIP_7D_WAVG

HOLD_SEC_DSKIP_7D_WAVG

DSKIP_RATE_7D

WAIT_SEC_DTONLY_7D_WAVG

HOLD_SEC_DTONLY_7D_WAVG

DTONLY_RATE_7D

STEP_SEC_7D_MED_NOT_ISKIP

AT_LEAST_ONE_HOLD_SEC_7D_AVG

AT_LEAST_ONE_HOLD_SEC_7D_MED

NUM_LOTS_MOVED_7D

QTY_MOVED_7D

SMP_RATE_7D

SMP_PCT_7D

ISKIP_PCT_7D

DSKIP_PCT_7D

STEP_SEC_7D_WAVG_NOT_ISKIP

STEP_SEC_COMP_7D_WAVG

STEP_SEC_7D_MED

NUM_JOBS_COMP_2D

QTY_COMP_2D

NUM_LOTS_ISKIP_2D

QTY_ISKIP_2D

NUM_LOTS_DSKIP_2D

QTY_DSKIP_2D

NUM_LOTS_DTONLY_2D

QTY_DTONLY_2D

TOTAL_STEP_SEC_2D

AVG_WIP_2D

WHY_PROC_2D

WHY_OTHERS_2D

WHY_SKIP_2D

STEP_SEC_2D_WAVG

HOLD_SEC_COMP_2D_WAVG

BLOCK_SEC_COMP_2D_WAVG

WAIT_SEC_COMP_2D_WAVG

DISP_SEC_COMP_2D_WAVG

PROC_SEC_COMP_2D_WAVG

ENDED_SEC_COMP_2D_WAVG

STEP_SEC_ISKIP_2D_WAVG

ISKIP_RATE_2D

WAIT_SEC_DSKIP_2D_WAVG

HOLD_SEC_DSKIP_2D_WAVG

DSKIP_RATE_2D

WAIT_SEC_DTONLY_2D_WAVG

HOLD_SEC_DTONLY_2D_WAVG

DTONLY_RATE_2D

NUM_LOTS_MOVED_2D

QTY_MOVED_2D

SMP_RATE_2D

SMP_PCT_2D

ISKIP_PCT_2D

DSKIP_PCT_2D

STEP_SEC_2D_WAVG_NOT_ISKIP

STEP_SEC_COMP_2D_WAVG

NUM_LOTS_ENDWIP

QTY_ENDWIP

IS_INACTIVE_STEP

Since we now use RTG_ROUTE_STEPS_INACTIVE table, we should only include the active steps on each route in RTG_ROUTE_STEPS. Therefore this value must be set to N in the RTG_ROUTE_STEPS table but will be set appropriately to Y for inactive steps in the RTG_ROUTE_STEPS_PLUS table. (* inherited from FPSINPUT.RTG_ROUTE_STEPS)

EST_SMP_PCT

Smp_pct tells you what percentage of the lots complete on a tool. Some sites skip steps by jumping over them so we see the lot move from step 3 to step 5 and we only know that it jumped step 4 because step 4 is on the route between 3 and 5. Other sites skip steps by moving lots into them and then moving them out a second later so we see a move from 3 to 4 at 11:11:11 and a move from 4 to 5 at 11:11:12. We do not care how it is done but just that the lot did not process at step 4 -- and to be more specific that no tool capacity is required to process this lot at step 4 and no cycle time is accumulated at step 4. (* inherited from FPSBASE.WIP_GOAL_LOT_SHIFT)

PROC_SEC_FOR_EOL

TCT_SEC

Theoretical cycle time in seconds (* inherited from FPSBASE.WIP_LOT_HIST)

UNIT_INT_SEC_FOR_EOL

EXPECTED_Q_SEC_COMP

FIFO_QUEUE_SEC

TARGET_QUEUE_SEC

COMMIT_QUEUE_SEC

FIFO_STEP_SEC

TARGET_STEP_SEC

COMMIT_STEP_SEC

STEP_SEC_NOHOLD_FOR_WSF

The FOR_WSF columns are used in populating WIP_STEP_FUTURE. This is based on the CTM_COLUMN_FOR_WIP_STEP_FUT column in GEN_FACILITIES. For example, if the value of that column is 7D_WAVG then we use the 7D_WAVG cycle times for WSF. (* inherited from FPSBASE.CTM_SUMMARY)

HOLD_SEC_FOR_WSF

HOLD_SEC_COMP_FOR_WSF

BLOCK_SEC_COMP_FOR_WSF

WAIT_SEC_COMP_FOR_WSF

DISP_SEC_COMP_FOR_WSF

PROC_SEC_COMP_FOR_WSF

ENDED_SEC_COMP_FOR_WSF

EST_LINE_YIELD_PCT

Estimated line yield percent for the route-step. Leave blank for the default of no loss expected. A value of 99.5 means we expected 1 unit out of 200 to be lost. (* inherited from FPSINPUT.RTG_ROUTE_STEPS)

EST_SORT_YIELD_PCT

Estimated sort yield percent for the product-step. Leave blank for the default of no loss expected. A value of 99.5 means we expected 1 unit out of 200 to be lost. (* inherited from FPSINPUT.RTG_PRD_STEP_OVR)

SEC_IN_FULL

SEC_IN_LONG

SEC_IN_7D

SEC_IN_2D

CTM_DATA_INST

86400

TOTAL_TARGET_CT_DAYS

86400

TOTAL_COMMIT_CT_DAYS

STEP_SEC_FULL_WAVG_TO_EOL

PROC_SEC_FULL_WAVG_TO_EOL

STEP_SEC_LONG_WAVG_TO_EOL

STEP_SEC_7D_WAVG_TO_EOL

STEP_SEC_7D_MED_TO_EOL

STEP_SEC_2D_WAVG_TO_EOL

TCT_SEC_TO_EOL

UNIT_INT_SEC_TO_EOL

The idea here is that a 1 wafer lot will progress a bit faster than a 25 wafer lot because it will save 24 wafer intervals at each step where wafers are processed individually. This column stores the number of seconds we expect to save for each wafer until the end of the line. In WIP_FLUSH we simply add or subtract this time based on whether the qty was higher or lower than the default in GEN_FACILITIES. We do not include lots which have been split in this adjustment since we expect they will be merged. For example, the CT to EOL is 30 days using our default of 20 wafers and this unit_int_sec_to_eol is 0.4 days. A lot with 19 wafers would get a revised estimate of 29.6. A lot with 18 wafers would get 29.2 and so on down to a lot with a single wafer at 22.4 days. On the other hand, our default can be less than the max so a lot with 21 wafers would get a revised estimate of 30.4 and so on up to a 25 wafer lot at 32 days. (* inherited from FPSBASE.CTM_SUMMARY)

FIFO_STEP_SEC_TO_EOL

This can be used for critical ratio to avoid the following situation. Lot A of prd A and lot B of prd B are both at the same step on the same route. Plan CT for A is 40 plan CT for B is 60. Due date for A is in 41 days. Due date for B is in 59 days. Normal CR says A is one day ahead and B is one day behind so run B first. But this is insane because both are on the same route with exactly the same steps coming up and B is only "behind" because of a lower expectation. We should run A first. If we use FIFO then both are something like 50 days CT and A is 9 days behind and B is 9 days ahead. However there is a problem with this strategy because we would basically let B sit around and do nothing for 20 days until it was also 40 days and then have to run it at the same rate. So this is not perfect either. (* inherited from FPSBASE.CTM_SUMMARY)

TARGET_STEP_SEC_TO_EOL

COMMIT_STEP_SEC_TO_EOL

STEP_SEC_NOHOLD_FOR_WSF_TO_EOL

This is the expected seconds from the current step to the end of line not including time on hold. WIP_STEP_FUTURE is used for upcoming arrivals and should predict as if the lot will not go on hold unless it is known that it will. The result is that the predictions are reasonably correct for lots that do not go on hold or where we know the future hold - but very wrong for a few lots that go on hold that we do not expect. In contrast, WIP_FLUSH which is used for prediction completion of the route and all future routes will use the entire STEP_SEC including average hold. (* inherited from FPSBASE.CTM_SUMMARY)

HOLD_SEC_FOR_WSF_TO_EOL

LINE_YIELD_PCT_TO_EOL

Line yield percentage to end of line is the percentage of units expected to successfully complete the remaining steps on the route. Normally we multiply the line yield of all remaining steps for the Capacity Model but entering a value in this OVR table manually overrides that calculated number. (* inherited from FPSINPUT.RTG_ROUTE_STEP_EQPTYPE_OVR)

SORT_YIELD_PCT_TO_EOL