FPSBASE.CTM_REF_SUMMARY_P2_BASE

Data Dictionary

FPSBASE Views

> FPSBASE.WIP_WAFER_HIST_LOOP

View FPSBASE.CTM_REF_SUMMARY_P2_BASE

This view collects the data from WIP_END_SHIFT_HIST and CTM_WEEK_HIST which is used to generate CTM_SUMMARY.

Column	Comment
FACILITY	Facility is included in almost every join in the DWH so this represents a definitive split. A route must have all steps on tools in the same facility. A tool must process all lots in the same facility. If your site has multiple buildings where lots run on routes using tools in multiple buildings then everything should be one facility. For example, multiple Fab buildings. But if your site has independent facilities like Fab and Test and Assembly where lot may progress from one to the next but on different routes then these should be different facilities. Since this column is in virtually every table it is critical that the value here is exactly matches what is in the MES if the MES has facility. Use facility_display for the display friendly name displayed in applications. See site_name comment for client/site/facility example. (* inherited from FPSINPUT.GEN_FACILITIES)
PRD	Prd determines the route which is used to process the lot in the facility and what tools, recipes, durables, etc. can be used at each step. Prd also determines the next facility for the lot when it finishes its route. For detailed information on prd vs. planprd see table comments in RTG_PLANPRDS. (* inherited from FPSINPUT.RTG_PRDS)
PLANPRD	Planning product used for all planning purposes. All lots with the same planprd are interchangeable to ship to the customer regardless of their prd, route, technology, wafer size, etc. For detailed information on prd vs. planprd see table comments in RTG_PLANPRDS. (* inherited from FPSINPUT.RTG_PLANPRDS)
ROUTE	Route that has threading requirements (* inherited from FPSINPUT.RTG_STEP_THREADING)
STEP	A single processing step within a route representing a single tool visit. Step is often a very complex string and should rarely be displayed. Instead we should use process_display. (* inherited from FPSINPUT.RTG_ROUTE_STEPS)
BANK	Lots which are not on a route are considered in a bank and the bank name indicates why the lot is off route. Bank must be NA for lots which are on a route. Our standard filter for active lots is bank = NA. (* inherited from FPSINPUT.RTG_BANKS)
PRTY_CTM_GROUP	This is one of the primary keys of our CTM tables. We use this group rather than the priority because we often have several different priorities which are close and are expected to have the same cycle time. (* inherited from FPSINPUT.WIP_PRIORITIES)
LOT_GROUP	Lot_group is a grouping of lot_family and is the highest grouping in the lot type hierarchy. There should be only a few values for lot_group, i.e. Prod, Dev, TW. We group WIP and moves by lot_group on the dashboard and we group cycle time calculations by lot_group so this is an important field. (* inherited from FPSINPUT.WIP_LOT_GROUPS)
IS_NONSTD	Our column to indicate non-standard processing at the step. For example, an experiment or a chain that is only active at a particular step or set of steps and then goes back to being normal for the route. If an experiment is severe enough that it affects the final product and has to be planned separately then it will be its own prd or planprd. (* inherited from FPSBASE.WIP_LOT_HIST)
NUM_JOBS_COMP_FULL
QTY_COMP_FULL
NUM_LOTS_ISKIP_FULL
QTY_ISKIP_FULL
NUM_LOTS_DSKIP_FULL
QTY_DSKIP_FULL
NUM_LOTS_RT_OR_PRD_FULL
QTY_RT_OR_PRD_FULL
NUM_LOTS_DTONLY_FULL
QTY_DTONLY_FULL
TOTAL_STEP_SEC_FULL
NUM_LOTS_MOVED_FULL
QTY_MOVED_FULL
TOTAL_HOLD_SEC_COMP_FULL
TOTAL_BLOCK_SEC_COMP_FULL
TOTAL_WAIT_SEC_COMP_FULL
TOTAL_DISP_SEC_COMP_FULL
TOTAL_PROC_SEC_COMP_FULL
TOTAL_ENDED_SEC_COMP_FULL
TOTAL_STEP_SEC_ISKIP_FULL
TOTAL_HOLD_SEC_DSKIP_FULL
TOTAL_WAIT_SEC_DSKIP_FULL
TOTAL_HOLD_SEC_RT_OR_PRD_FULL
TOTAL_WAIT_SEC_RT_OR_PRD_FULL
TOTAL_HOLD_SEC_DTONLY_FULL
TOTAL_WAIT_SEC_DTONLY_FULL
NUM_JOBS_COMP_LONG
QTY_COMP_LONG
NUM_LOTS_ISKIP_LONG
QTY_ISKIP_LONG
NUM_LOTS_DSKIP_LONG
QTY_DSKIP_LONG
NUM_LOTS_RT_OR_PRD_LONG
QTY_RT_OR_PRD_LONG
NUM_LOTS_DTONLY_LONG
QTY_DTONLY_LONG
TOTAL_STEP_SEC_LONG
NUM_LOTS_MOVED_LONG
QTY_MOVED_LONG
TOTAL_HOLD_SEC_COMP_LONG
TOTAL_BLOCK_SEC_COMP_LONG
TOTAL_WAIT_SEC_COMP_LONG
TOTAL_DISP_SEC_COMP_LONG
TOTAL_PROC_SEC_COMP_LONG
TOTAL_ENDED_SEC_COMP_LONG
TOTAL_STEP_SEC_ISKIP_LONG
TOTAL_HOLD_SEC_DSKIP_LONG
TOTAL_WAIT_SEC_DSKIP_LONG
TOTAL_HOLD_SEC_RT_OR_PRD_LONG
TOTAL_WAIT_SEC_RT_OR_PRD_LONG
TOTAL_HOLD_SEC_DTONLY_LONG
TOTAL_WAIT_SEC_DTONLY_LONG
NUM_JOBS_COMP_7D
QTY_COMP_7D
NUM_LOTS_ISKIP_7D
QTY_ISKIP_7D
NUM_LOTS_DSKIP_7D
QTY_DSKIP_7D
NUM_LOTS_RT_OR_PRD_7D
QTY_RT_OR_PRD_7D
NUM_LOTS_DTONLY_7D
QTY_DTONLY_7D
TOTAL_STEP_SEC_7D
NUM_LOTS_MOVED_7D
QTY_MOVED_7D
TOTAL_HOLD_SEC_COMP_7D
TOTAL_BLOCK_SEC_COMP_7D
TOTAL_WAIT_SEC_COMP_7D
TOTAL_DISP_SEC_COMP_7D
TOTAL_PROC_SEC_COMP_7D
TOTAL_ENDED_SEC_COMP_7D
TOTAL_STEP_SEC_ISKIP_7D
TOTAL_HOLD_SEC_DSKIP_7D
TOTAL_WAIT_SEC_DSKIP_7D
TOTAL_HOLD_SEC_RT_OR_PRD_7D
TOTAL_WAIT_SEC_RT_OR_PRD_7D
TOTAL_HOLD_SEC_DTONLY_7D
TOTAL_WAIT_SEC_DTONLY_7D
NUM_JOBS_COMP_2D
QTY_COMP_2D
NUM_LOTS_ISKIP_2D
QTY_ISKIP_2D
NUM_LOTS_DSKIP_2D
QTY_DSKIP_2D
NUM_LOTS_RT_OR_PRD_2D
QTY_RT_OR_PRD_2D
NUM_LOTS_DTONLY_2D
QTY_DTONLY_2D
TOTAL_STEP_SEC_2D
NUM_LOTS_MOVED_2D
QTY_MOVED_2D
TOTAL_HOLD_SEC_COMP_2D
TOTAL_BLOCK_SEC_COMP_2D
TOTAL_WAIT_SEC_COMP_2D
TOTAL_DISP_SEC_COMP_2D
TOTAL_PROC_SEC_COMP_2D
TOTAL_ENDED_SEC_COMP_2D
TOTAL_STEP_SEC_ISKIP_2D
TOTAL_HOLD_SEC_DSKIP_2D
TOTAL_WAIT_SEC_DSKIP_2D
TOTAL_HOLD_SEC_RT_OR_PRD_2D
TOTAL_WAIT_SEC_RT_OR_PRD_2D
TOTAL_HOLD_SEC_DTONLY_2D
TOTAL_WAIT_SEC_DTONLY_2D
NUM_LOTS_ENDWIP
QTY_ENDWIP
STEP_SEC_7D_MED_NOT_ISKIP_R
NUM_LOTS_AT_LEAST_ONE_HOLD_7D
QTY_AT_LEAST_ONE_HOLD_7D
AT_LEAST_ONE_HOLD_SEC_7D_AVG_R
AT_LEAST_ONE_HOLD_SEC_7D_MED_R
SEQ_NUM	Sequence number of step in route (* inherited from FPSINPUT.RTG_ROUTE_STEPS)
REVERSE_SEQ_NUM
IS_INACTIVE_STEP	Since we now use RTG_ROUTE_STEPS_INACTIVE table, we should only include the active steps on each route in RTG_ROUTE_STEPS. Therefore this value must be set to N in the RTG_ROUTE_STEPS table but will be set appropriately to Y for inactive steps in the RTG_ROUTE_STEPS_PLUS table. (* inherited from FPSINPUT.RTG_ROUTE_STEPS)
TCT_SEC	Theoretical cycle time in seconds (* inherited from FPSBASE.WIP_LOT_HIST)
UNIT_INT_SEC
COMMON_STEP	A display-friendly field that groups similar steps together for purposes of viewing the entire line. Typically the only duplicates within a single route will be optional ordered steps in the same segment. But we will often have steps across routes that share the same common step even though exact step definition is not identical. (* inherited from FPSINPUT.RTG_COMMON_STEPS)
STEP_OR_COMMON_STEP
PROCESS	Process defines what occurs at a step. Different steps can share the same process if they are identical. Process should normally determine allowed tools and recipe although it can be overridden by step, route, prd, lot, and experiment for exceptions. Each process is dynamically assigned to one or more eqp_type-process_family combinations with use_pct. One process_family is determined to be primary. If grouping is done correctly, a process should only be one eqp_group with no crossover. (* inherited from FPSINPUT.RTG_PROCESSES)
PROCESS_FAMILY	See https://help.inficonims.com/display/DW/Guide+to+Process+Families. (* inherited from FPSINPUT.RTG_PROCESS_FAMILIES)
PROCESS_MODULE	WIP_MODULE is used to credit moves and set goals. See comments on the module column in GEN_MODULES for info on this column and how it relates to eqp_module and mnt_module. (* inherited from FPSBASE.RTG_ROUTE_STEPS_PLUS)
PROCESS_CLASS	Top-level grouping of process groups with same general purpose (i.e. Process or Metrology or Nonwafer). Allowed values are defined by FPS and are listed in FPSADMIN.RTG_PROCESS_CLASSES. This field can also be defined in EQP_TOOLS using the ovr_process_class field if we do not know it for the process group. (* inherited from FPSINPUT.RTG_PROCESS_GROUPS)
LINE_SECTION	Large grouping of the line, e.g. FEOL, BEOL, Cu, etc. There should be only a handful of values for the entire facility - or if the facility only has one section then we can leave this column blank. (* inherited from FPSINPUT.RTG_LINE_SECTIONS)
ROUTE_SEGMENT	Route_segment allows for clear hierarchical segment organization for Segment Summary and Line Viewer on Dashboard. This is often referred to as stage and typically will come from the MES (as opposed to facility_segment which we will typically have to define for our purposes). We recommend that all routes in the same route family have the same route segments in the same order so that the Line Viewer by route family will be consistent but if this is not the case then we approximate the order as best we can. (* inherited from FPSINPUT.RTG_ROUTE_STEPS)
ROUTE_FAMILY	Route_family indicates that all routes within the family have similar or even identical steps and have the same segments. At facilities where various prds share the same route it is likely that the route will be the route_family. This is sometimes referred to as the main process flow. It is used on Segment Summary and Line Viewer to group similar routes. (* inherited from FPSINPUT.RTG_ROUTE_FAMILIES)
ROUTE_FAMILY_IF_USED_IN_G1
LOT_GROUP_IF_USED_IN_G1
ROUTE_GROUP	Route_group is the parent of route_family. Route_group is used on the Dashboard and other applications as a large grouping for filtering. At many sites this is referred to as technology. (* inherited from FPSINPUT.RTG_ROUTE_GROUPS)
WAFER_SIZE	If the facility only has one wafer size then this column should be null in both RTG_PRDS and EQP_TYPES. If the facility has more than one wafer size then a value of null in EQP_TYPES means that those tools can run all wafer sizes. See column IS_ANY_WAFER_SIZE for details. (* inherited from FPSINPUT.GEN_WAFER_SIZES)
IS_MAIN_ROUTE	Y indicates the route is the main processing route for PRD. N indicates it is a rework or alternate route. (* inherited from FPSBASE.RTG_ACTIVE_PRD_ROUTES_BASE)
IS_STAGING_STEP	We expect large amounts of WIP and long cycle times at staging steps. We still calculate cycle time like any other step but the important difference is that lots currently at a staging step are not counted as normal coming lots to future steps. Instead we show them in a special column labeled From Staging. (* inherited from FPSINPUT.RTG_ROUTE_STEPS)
OVR_TARGET_STEP_SEC	We normally automatically calculate commit/target cycle times by weighting across steps based on historical information so that the total for the route equals the specified total for commit/target in RTG_PRDS. This column along with ovr_commit_step_sec allows us to override that automated calculation for certain route-steps with a specific value. We encourage leaving these columns blank. (* inherited from FPSINPUT.RTG_ROUTE_STEPS)
OVR_COMMIT_STEP_SEC	See comments in OVR_TARGET_STEP_SEC column. (* inherited from FPSINPUT.RTG_ROUTE_STEPS)
OVR_STEP_SEC_FOR_FUT	For WIP_STEP_FUTURE cycle time predictions, we normally use the automatically calculated cycle time from CTM_SUMMARY as configured in ctm_column_for_wip_step_fut from GEN_FACILITIES (i.e. FULL, COMMIT, 7D_MED, 2D_WAVG, etc.). The ovr_step_sec_for_fut columns in RRS and WIP_STEP_FUTURE_OVR allow us to override this value with a manual value for a specified route-step or a specified lot-route-step. The ovr column from RRS is used in the CTM_SUMMARY logic so it will be the value of step_sec_nohold_for_wsf and step_sec_for_wsf_if_take in CTM_SUMMARY and RTG_ROUTE_STEPS_PLUS as well as the value in WIP_STEP_FUTURE. The ovr column from WSF_OVR is specific to the lot and therefore is only used in UPDATE_WIP_STEP_FUTURE so you will only see this value in WIP_STEP_FUTURE. In addition, a value in WSF_OVR indicates that the lot will TAKE at this step. If both are populated, WSF will use the more specific value by lot from WSF_OVR. The most common use of this column is to override the 10 second default for staging steps used by the Scheduler. Other than staging steps, we recommend using these overrides rarely. (* inherited from FPSINPUT.RTG_ROUTE_STEPS)
SMP_PCT_VALID_LOTS_2D	Minimum number of lots over the 2 day period required for 2 day sample pct to be considered valid. This number includes both moved lots and lots in WIP at the end of the period. In addition you must have at least one lot moved. (* inherited from FPSINPUT.GEN_FACILITIES)
SMP_PCT_VALID_LOTS_7D	Minimum number of lots over the 7 day period required for 7 day sample pct to be considered valid. This number includes both moved lots and lots in WIP at the end of the period. In addition you must have at least one lot moved. (* inherited from FPSINPUT.GEN_FACILITIES)
SMP_PCT_VALID_LOTS_LONG	Minimum number of lots over the number of weeks defined in ctm_long_window_weeks required for long sample pct to be considered valid. This number includes both moved lots and lots in WIP at the end of the period. In addition you must have at least one lot moved. (* inherited from FPSINPUT.GEN_FACILITIES)
SMP_PCT_VALID_LOTS_FULL	Minimum number of lots over the number of weeks defined in ctm_full_window_weeks required for full sample pct to be considered valid. This number includes both moved lots and lots in WIP at the end of the period. In addition you must have at least one lot moved. (* inherited from FPSINPUT.GEN_FACILITIES)
CTM_VALID_LOTS_2D	Minimum number of lots over the 2 day period required for 2 day cycle time to be considered valid. This number includes both moved lots and lots in WIP at the end of the period. In addition you must have at least one lot moved. (* inherited from FPSINPUT.GEN_FACILITIES)
CTM_VALID_LOTS_7D	Minimum number of lots over the 7 day period required for 7 day cycle time to be considered valid. This number includes both moved lots and lots in WIP at the end of the period. In addition you must have at least one lot moved. (* inherited from FPSINPUT.GEN_FACILITIES)
CTM_VALID_LOTS_LONG	Minimum number of lots over the number of weeks defined in ctm_long_window_weeks required for long cycle time to be considered valid. This number includes both moved lots and lots in WIP at the end of the period. In addition you must have at least one lot moved. (* inherited from FPSINPUT.GEN_FACILITIES)
CTM_VALID_LOTS_FULL	Minimum number of lots over the number of weeks defined in ctm_full_window_weeks required for full cycle time to be considered valid. This number includes both moved lots and lots in WIP at the end of the period. In addition you must have at least one lot moved. (* inherited from FPSINPUT.GEN_FACILITIES)
CTM_COLUMN_FOR_WIP_STEP_FUT	This tells our WIP_STEP_FUTURE logic which column to use from CTM_SUMMARY to estimate cycle time to future steps. FULL and LONG are configurable in GEN_FACILITIES but usually 4 weeks and 2 weeks except for small fabs where we make them longer. These as well as 7D and 2D are weighted averages for only time during the period. TARGET and COMMIT are two varieties of plan cycle time. The total for each prd is set by the client via ETL in RTG_PRDS then we adjust the wait time of each step so that the total CT adds up to the total for the prd in a reasonably intelligent balance based on the history. For example, if history was 20 days proc and 50 days wait and commit is 60 then we multiply the wait time of each step by 4/5 so the total wait adds up to 40 and the total cycle time adds up to the commit value of 60. FIFO is the average for the entire process family so this represents what the cycle time would be if we ran the entire fab in FIFO order without any priority. (* inherited from FPSINPUT.GEN_FACILITIES)
CTM_COLUMN_FOR_EST_SMP_PCT	This tells our CTM_SUMMARY logic which column to use to estimate sampling percentage. This is either FULL or LONG or 7D. The Dashboard hover message shows this configuration but it is not linked so if you change this column then you need to update DASH_C_CATEGORY_TABLE_COLS to match using the query from DWH-2030. (* inherited from FPSINPUT.GEN_FACILITIES)
NONSTD_CTM_FACTOR	Factor to multiply cycle time if non-standard compared to standard is not known. For example, if this is 1.5 and we know the standard CTM is 6 hours and we do not know the non-standard CTM then we would estimate it to be 9 hours. (* inherited from FPSINPUT.GEN_FACILITIES)
LOTGRP_CTM_FACTOR
MIN_STEP_SEC	See MAX_STEP_SEC comment. This minimum limit should rarely be used. (* inherited from FPSINPUT.RTG_PROCESS_FAMILIES)
MAX_STEP_SEC	This is a cap on the cycle time for steps in this process family. The most common use is for a process family which has historically been bad but we do not want the cycle time to show that. We hesitated on capping the historical numbers and prefer to only cap commit and target but we somewhat reluctantly agreed to cap history too. (* inherited from FPSINPUT.RTG_PROCESS_FAMILIES)
MAX_DEFAULT_STEP_SEC
PRTY_CTM_FACTOR	Factor to multiply cycle time for this priority group compared to other groups if not known. For example, if this factor is 1.5 and we know the CTM is 6 hours for another priority group whose factor is 1.0 then we would estimate it to be 9 hours for this group. (* inherited from FPSINPUT.WIP_PRTY_CTM_GROUPS)
MAX_HOLD_SEC_FOR_WSF	Prevent huge cycle times at steps where a minority of lots have been on hold for an exceedingly long time (* inherited from FPSINPUT.WIP_PRTY_CTM_GROUPS)
MAX_STEP_SEC_NOHOLD_FOR_WSF	Prevent huge cycle times at steps where a minority of lots have been waiting for an exceedingly long time (* inherited from FPSINPUT.WIP_PRTY_CTM_GROUPS)
USE_CTM_FACTOR_IF_OVR
TOTAL_TARGET_CT_DAYS_W_NULL
TOTAL_COMMIT_CT_DAYS_W_NULL
EST_LINE_YIELD_PCT	Estimated line yield percent for the route-step. Leave blank for the default of no loss expected. A value of 99.5 means we expected 1 unit out of 200 to be lost. (* inherited from FPSINPUT.RTG_ROUTE_STEPS)
EST_SORT_YIELD_PCT	Estimated sort yield percent for the product-step. Leave blank for the default of no loss expected. A value of 99.5 means we expected 1 unit out of 200 to be lost. (* inherited from FPSINPUT.RTG_PRD_STEP_OVR)
DEFAULT_PROC_SEC_COMP
DEFAULT_WAIT_SEC
DEFAULT_BANK_SEC
SEC_IN_2D
SEC_IN_7D
SEC_IN_LONG
SEC_IN_FULL
CTM_DATA_INST
QTY_UNIT	Defines the unit used to measure number of quantity. The key here is that this quantity must be known throughout the entire route through the facility. For example in a sort facility where lots enter in wafers and are broken into die but the number of wafers is still known when the lot completes the facility then the qty_unit must be wafer. It cannot be die because die is not known when the lot enters so die will be the sec_qty_unit. Similarly at a final test facility where the lots enter with both wafers and die known but only die are known when the lot completes the facility then the qty_unit must be die. It cannot be wafer because wafer is not known when the lot completes so wafer will be the sec_qty_unit. Please note the entire process from only wafers to only die must be split into at least two facilities because of this requirement. (* inherited from FPSINPUT.GEN_FACILITIES)
DEFAULT_PROC_CT_SEC	See comment on DEFAULT_WAIT_CT_SEC column. (* inherited from FPSINPUT.GEN_FACILITIES)
DEFAULT_WAIT_CT_SEC	The default cycle time for miscellaneous steps that are in process families with no valid cycle time are 10 minutes processing and 20 minutes waiting for a total of 30 minutes. This column along with default_proc_ctm_sec allows us to change these defaults. The most likely change would be to 0 seconds processing and 1 second waiting to essentially ignore all miscellaneous steps. (* inherited from FPSINPUT.GEN_FACILITIES)
EST_BAY_FOR_TRANSIT
PREV_EST_BAY_FOR_TRANSIT
EST_TRANSIT_SEC